1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (63/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
- Data Setup, Hold, and Slew Rate De-rating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet
tDS(base) and tDH(base) value to the ΔtDS and ΔtDH derating value respectively.
Example: tDS (total setup time) = tDS(base) + ΔtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and
the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the
nominal slew rate line between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual
signal is later than the nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the
tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tDH) nominal slew rate
for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of
Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line
between shaded ‘dc level to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier
than the nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to
the actual signal from the dc level to Vref(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 43. Data Setup and Hold Base - Values
Symbol
Reference
-12
Unit
t_DS(base) AC135
V_IH/L(ac)
25
ps
t_DH(base) DC90
V_IH/L(dc)
55
ps
NOTE 1: (ac/dc referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)
Table 44. Derating values for DDR3L-1600 tDS/tDH – (AC135)
△t_DS, △t_DH derating in [ps] AC/DC based
DQS, DQS# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH
DQ 2.0 68 45 68 45 68 45
-
-
-
-
-
-
-
-
-
-
Slew _{1.5 45}
30
45
30
45
30
53
38
-
-
-
-
-
-
-
-
Rate _1.0
0
0
0
0
0
0
8
8
16 16
-
-
-
-
-
-
V/ns _0.9
-
-
2
-3
2
-3
10
5
18 13 26 21
-
-
-
-
0.8
-
-
-
-
3
-8
11
1
19
9
27 17 35 27
-
-
0.7
-
-
-
-
-
-
14
-5
22
3
30 11 38 21 46 37
0.6
-
-
-
-
-
-
-
-
25
-4
33
4
41 14 49 30
0.5
-
-
-
-
-
-
-
-
-
-
29
-6
37
4
45 20
0.4
-
-
-
-
-
-
-
-
-
-
-
-
30 -11 38
5
Confidential
63
Rev. 2.0
Aug. /2014