1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (78/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
Figure 57. Power-Down Entry after Write with Auto Precharge
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
Tb2
Tc0
Tc1
CK#
CK
COMMAND
WRITE
NOP
CKE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tIS ^tCPDED
NOP
VALID
VALID
ADDRESS
A10
Bank,
Col n
WL = AL + CWL
WR ^{Notes 1}
VALID
tPD
DQS, DQS#
DQ BL8
DQ BC4
NOTES:
1. WR is programmed through MR0.
Din
Din
Din
Din
Din
Din
Din
Din
b
b+1
b+2
b+3
b+4
b+5
b+6
b+7
Start Internal
Din
Din
Din
Din
b
b+1
b+2
b+3
tWRAPDEN
Precharge
Power - Down
Entry
TIME BREAK
TRANSITIONING DATA
Don't Care
Figure 58. Power-Down Entry after Write
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
CK#
CK
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
Ta6
Ta7
NOP
NOP
Tb0
Tb1
Tb2
NOP
NOP
NOP
tIS ^tCPDED
Tc0
Tc1
NOP
VALID
VALID
ADDRESS
A10
Bank,
Col n
WL = AL + CWL
VALID
tWR
tPD
DQS, DQS#
DQ BL8
DQ BC4
Din
Din
Din
Din
Din
Din
Din
Din
b
b+1
b+2
b+3
b+4
b+5
b+6
b+7
Din
Din
Din
Din
b
b+1
b+2
b+3
tWRPDEN
Power - Down
Entry
TIME BREAK
TRANSITIONING DATA
Don't Care
Confidential
78
Rev. 2.0
Aug. /2014