AK4955 Datasheet, PDF (86/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
Addr
04H
Register Name
Signal Select 3
R/W
Default
D7
MONO1
R/W
0
D6
MONO0
R/W
0
D5
LOPS
R/W
0
D4
DACL
R/W
0
D3
BEEPL
R/W
0
D2
D1
D0
0
LVCM1 LVCM0
R
R/W
R/W
0
0
1
LVCM1-0: Stereo Line Output Gain and Common Voltage Setting (Table 58)
BEEPL: Signal Switch Control from the MIN pin to Lineout
0: OFF (default)
1: ON
DACL: DAC Output Signal to Stereo Line Amp Control
0: OFF (default)
1: ON
When PMLO bit = “1”, this bit setting is enabled. LOUT and ROUT pins output VSS1 when PMLO bit = “0”.
LOPS: Stereo Line Output Power Save
0: Normal Operation (default)
1: Power Save Mode
MONO1-0: LOUT/ROUT Output Signal Mode Select (Table 59)
Addr
05H
Register Name
Mode Control 1
R/W
Default
D7
D6
D5
D4
D3
D2
PLL3 PLL2 PLL1 PLL0 BCKO
0
R/W
R/W
R/W
R/W
R/W
R
1
1
0
0
0
0
DIF1-0: Audio Interface Format (Table 17)
Default: “10” (MSB justified)
BCKO: Master Mode BICK Output Frequency Setting (Table 15)
PLL3-0: PLL Reference Clock Select (Table 4)
Default: “1100”
D1
DIF1
R/W
1
D0
DIF0
R/W
0
Addr
06H
Register Name
Mode Control 2
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
PS1
PS0
FFTE DSPC
FS3
FS2
FS1
FS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
FS3-0: Sampling Frequency (Table 5, Table 6) and MCKI Frequency Setting (Table 11)
These bits control sampling frequency in PLL mode, and MCKI frequency in EXT mode.
DSPC: DSP Clock Select
0: 256fs (default)
1: 512fs
FFTE: FFT, iFFT Circuit Power Management
0: Power down (default)
1: Power up
PS1-0: MCKO Frequency Setting (Table 9)
Default: “00” (256fs)
MS1343-E-00
- 86 -
2011/12