AK4955 Datasheet, PDF (74/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

2. RAM Reading Timing during RST (when DSPSTBN bit= “1” and PMDSP bit= “0”).
[AK4955]
DSPSTBN bit
PMDSP bit
CSN
(control register setting is abbreviated)
CCLK
CDTIO
don’tcare
(L/H)
Command Address WAIT DATA DATA DATA
Figure 65. RAM Reading Timing during RST
DATA
don’tcare
(L/H)
RAM data can be readout during a reset.
There is a wait time (1byte) after command code and address inputs when reading RAM data. During this wait time, the
CDTIO pin is in output state and the output data is indefinite. MSB data is output on the first falling edge of CCLK after
the wait time.
Command code and Output data length are shown below.
Command ^Description
Address
Length
7EH
CRAM reading during RST.
2byte
Data
Length
2byte
Note
Only the first read address is necessary when
reading from consecutive address data.
7FH
PRAM reading during RST.
2byte
5byte
Table 65. Command Code and Output Data in RAM Reading during a RST
MS1343-E-00
- 74 -
2011/12