AK4955 Datasheet, PDF (51/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
Register Name
LMTH1-0
ZELMN
FRN
ZTM1-0
WTM2-0
OREF5-0
OVL7-0,
OVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC2
Comment
fs=8kHz
Data
Operation
Limiter detection Level
01
−4.1dBFS
Limiter zero crossing detection
0
Enable
Fast Recovery mode
0
Enable
Zero crossing timeout period
01
32ms
Recovery waiting period
*WTM2-0 bits should be the same
value or larger value than ZTM1-0
001
32ms
bits
Maximum gain at recovery operation 28H
+6dB
Gain of VOL
91H
0dB
Limiter ATT step
00
1 step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
Fast Recovery Speed
01
4 times
ALC2 enable
1
Enable
Table 37. Example of the ALC Setting (Playback)
fs=48kHz
Data
Operation
01
−4.1dBFS
0
Enable
0
Enable
11
21.3ms
100
42.7ms
28H
+6dB
91H
0dB
00
1 step
1
ON
00
1 step
01
4 times
1
Enable
5. Example of registers set-up sequence of ALC Operation
The following registers must not be changed during ALC operation. These bits must be changed after ALC operation is
stopped by ALC1 bit = ALC2 bit= “0”. ALC output is “0” data until the AK4955 becomes manual mode after writing “0”
to ALC1 and ALC2 bits.
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN 1-0, REF7-0, ZELMN, RFST1-0, LFST, FRN bits
Manual Mode
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 42.7ms@48kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC1 bit = “1”
WR (FRN, ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=0AH, Data=73H
WR (IREF7-0)
(2) Addr=0CH, Data=E1H
WR (IVL/R7-0) ^{* The value of IVOL should be}
the same or smaller than REF’s
WR (RGAIN1-0)
(3) Addr=0FH&10H, Data=E1H
(4) Addr=0DH, Data=28H
WR (LFST, ZELMN, LMAT1-0, LMTH1-0; ALC1= “1”)
(5) Addr=0BH, Data=A1H
ALC1 Operation
Figure 43. Registers Set-up Sequence at ALC1 Operation (recording path)
MS1343-E-00
- 51 -
2011/12