AK4955 Datasheet, PDF (68/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
■ Serial Control Interface
(1) 3-wire Serial Control Mode (00H ~ 4FH)
1. Data Writing and Reading Modes on Every Address (00H~4FH)
One data is written to (read from) one address.
Internal registers may be written by using 3-wire serial interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control data or Output data (MSB first, 8bits).
Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. Data writings
become available on the rising edge of CSN. When reading the data, the CDTIO pin changes to output mode at the falling
edge of 8th CCLK and outputs data in D7-D0. However this reading function is available only when READ bit = “1”.
When READ bit = “0”, the CDTIO pin stays as Hi-Z even after the falling edge of 8th CCLK. The data output finishes on
the rising edge of CSN. The CDTIO is placed in a Hi-Z state except when outputting the data at read operation mode.
Clock speed of CCLK is 12.5MHz (max) when writing and 6.75MHz (max) when reading. The value of internal registers
are initialized by the PDN pin = “L”.
Note 50. Data reading is only available on the following addresses; 00 ~ 4FH and 50H ~ 6FH. When reading address 50H
~ 6FH, the register values are invalid.
CSN
CCLK _{“H” or “L”}
0 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
“H” or “L”
CDTIO “H” or “L”
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
R/W:
A6-A0:
D7-D0:
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 55. Serial Control Interface Timing 1
MS1343-E-00
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2011/12