AK4955 Datasheet, PDF (30/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4955 becomes EXT mode. Master clock can be input to the internal ADC and DAC
directly from the MCKI pin without internal PLL circuit operation. This mode is compatible with I/F of a normal audio
CODEC. The external clocks required to operate this mode are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK
(≥32fs). The master clock (MCKI) must be synchronized with LRCK. The phase between these clocks is not important.
The input frequency of MCKI is selected by FS1-0 bits (Table 11).
Mode
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
0
x
0
0
256fs
7.35kHz ∼ 48kHz (default)
1
x
0
1
1024fs
7.35kHz ∼ 13kHz
2
x
1
0
512fs
7.35kHz ∼ 26kHz
3
x
1
1
512fs
7.35kHz ∼ 48kHz
(x: Don’t care)
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through
LOUT/ROUT pins is shown in Table 12.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
Mode0: 256fs
Mode3: 512fs
80dB
Mode2: 512fs
92dB
Mode1: 1024fs
92dB
Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins
AK4955
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
256fs, 512fs or 1024fs
DSP or μP
MCLK
≥ 32fs
BCLK
1fs
LRCK
SDTI
SDTO
Figure 21. EXT Slave Mode
MS1343-E-00
- 30 -
2011/12