AK4955 Datasheet, PDF (110/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
■ Beep Signal Output from Speaker-Amp
BEEP Gen bits _XXH
(Addr:15-19H)
PMSPK bit
(Addr:00H, D4)
PMBP bit
(Addr:01H, D4)
SPPSN bit
(Addr:01H, D7)
BPOUT bit
(Addr:19H, D7)
X
(1)
YYH
(2)
(3)
(4)
> 1 ms
0
(5)
1
(8)
(7)
(6)
0
SPP pin
Hi-Z
SVDD/2 Beep Output SVDD/2
Hi-Z
SPN pin
Hi-Z SVDD/2
Beep Output SVDD/2
Hi-Z
Example:default
(1) Addr:15-19H, Data:YYH
Addr:19H,D7, BPOUT bit =“0”
(2) Addr:00H, Data:50H
(3) Addr:01H, Data:20H
(4) Addr:01H, Data:A0H
(5) Addr:19H, Data:80H
BEEP Signal Output
Addr:19H, Data:00H (Auto)
(6) Addr:01H, Data:20H
(7) Addr:01H, Data:00H
(8) Addr:00H, Data:40H
Figure 87. “BEEP Generator → Speaker-Amp” Output Sequence
<Example>
At first, clocks must be supplied according to “Clock Set Up” sequence.
When the AK4955 is PLL mode, Speaker-Amp of (2) and BEEP Generator of (3) must be powered-up in
consideration of PLL lock time after a sampling frequency is changed.
(1) Set up BEEP Generator (Addr: 15H ~ 19H) (BPOUT bit must be set to “0”.)
(2) Power up Speaker: PMSPK bit = “0” → “1”
(3) Power up BEEP Generator: PMBP bit = “0” → “1”
(4) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(5) BEEP output: BPOUT bit= “0” → “1”
After outputting data determined set times, BPOUT bit automatically returns to “0”.
(6) Enter Speaker-Amp Power-save-mode: SPPSN bit = “1” → “0”
(7) Power down BEEP Generator: PMBP bit = “1” → “0”
(8) Power down Speaker: PMSPK bit = “1” → “0”
MS1343-E-00
- 110 -
2011/12