AK4955 Datasheet, PDF (107/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
■ MIC Input Recording (Stereo)
FS3-0 bits
(Addr:06H, D3-0)
MIC Control
(Addr:02H)
Timer Select
(Addr:09H, D7-6
Addr:0AH)
0000
(1)
06H
(2)
00, 00H
(3)
ALC Control 2 _E1H
(Addr:0CH )
(4)
IVL7-0 bits
(Addr:0FH)
ALC Control 3
(Addr:0DH, D7-6)
E1H
00
(5)
(6)
ALC Control 1
(Addr:0BH)
Digital Filter Path
(Addr:1DH)
Filter Co-ef
(Addr:1CH,1E-25H,
32-4FH)
00H
03H
XX....X
(7)
(8)
(9)
1011
E6H
00, 70H
E1H
E1H
00
A1H
03H
XX....X
Filter Select
(Addr:1CH, 30H)
ALC1 State
XX....X
(10)
ALC1 Disable
XX....X
ALC1 Enable
PMPFIL bit
PMADL/R bit
(Addr:00H, D7, D1-0)
(11) _1059/fs
00H
(13)
ALC1 Disable
(12)
SDTO pin
State
0 data Output
Normal
Initialize _{Data Output} 0 data output
Example:
PLL Master Mode
Audio I/F Format: MSB justified
Pre MIC Amp: +18dB
MIC Power 1 ON
Sampling Frequency: 48kHz
ALC1 setting: Refer to Table 36
HPF1: fc=118.4Hz, ADRST1-0 bits = “00”
Programmable Filter OFF
(1) Addr:06H, Data:0BH
(2) Addr:02H, Data:E6H
(3) Addr:09H, Data:00H
Addr:0AH, Data:71H
(4) Addr:0CH, Data:E1H
(5) Addr:0FH, Data:E1H
(6) Addr:0DH, Data:00H
(7) Addr:0BH, Data:A1H
(8) Addr:1DH, Data:03H
(9) Addr:1BH, Data:04H
(10) Addr:1BH, Data:05H
(11) Addr:00H, Data:C3H
Recording
(12) Addr:00H, Data:40H
(13) Addr:0BH, Data:81H
Figure 84. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=48kHz. For changing the parameter of ALC, please refer to Table
36”. At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4955 is the PLL mode, MIC, ADC and Programmable
Filter of (11) must be powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC Amp and MIC Power. (Addr = 02H)
(3) Set up ALC1 Timer, ADRST1-0 bits (Addr = 09H, 0AH)
(4) Set up IREF value at ALC1 (Addtr = 0CH)
(5) Set up IVOL value at ALC1 operation start (Addr = 0FH)
(6) Set up RGAIN1-0 bits (Addr =0DH)
(7) Set up LMTH1-0, LMAT1-0, ZELMN, ALC1 and LFST bits (Addr = 0BH)
(8) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1” (Addr = 1DH)
(9) Set up Coefficient Programmable Filter (Addr: 1CH, 1EH ~ 25H, 32H ~ 4FH)
(10) Set up of Programmable Filter ON/OFF
(11) Power Up ADC and Programmable Filter: PMADL =PMADR =PMPFIL bits = “0” →“1”
The initialization cycle time of ADC is 1059/fs=22ms @ fs=48kHz, ADRST1-0 bit = “00”. ADC outputs “0”
data during the initialization cycle. After the ALC1 bit is set to “1”, the ALC1 operation starts from IVOL
value of (5).
(12) Power Down ADC and Programmable Filter: PMADL = PMADR = PMPFIL bits = “1” → “0”
(13) ALC Disable: ALC1 bit = “1” → “0”
MS1343-E-00
- 107 -
2011/12