AK4955 Datasheet, PDF (69/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
2. Continuous Data Writing Mode (00H~4FH)
Address is incremented automatically and data is written continuously. This mode does not support reading. When the
written address reaches 4FH, it is automatically incremented to 00H. Writing to the address 0EH and 31H are ignored.
In this mode, registers are written by 3-wire serial interface pins (CSN, CCLK and CDTIO). The data on the 3-wire serial
interface is 8 bit data, consisting of register address (MSB-first, 7bits) and control or output data (MSB-first, 8xN bits)).
The receiving data is latched on a rising edge (“↑”) of CCLK. The first write data becomes effective between the rising
edge (“↑”) and the falling edge (“↓”) of 16th CCLK. When the micro processor continues sending CDTI and CCLK
clocks while the CSN pin = “L”, the address counter is incremented automatically and writing data becomes effective
between the rising edge (“↑”) and the falling edge (“↓”) of every 8th CCLK. For the last address, writing data becomes
effective between the rising edge (“↑”) of 8th CCLK and the rising edge (“↑”) of CSN. The clock speed of CCLK is
12.5MHz (max). The internal registers are initialized by the PDN pin = “L”.
Even through the writing data does not reach the last address; a write command can be completed when the CSN pin is set
to “H”.
Note 51. When CSN “↑” was written before “↑” of 8th CCLK in continuous data writing mode, the previous data writing
address becomes valid and the writing address is ignored.
Note 52. After 8bits data in the last address became valid, put the CSN pin “H” to complete the write command. If the
CDTI and CCLK inputs are continued when the CSN pin = “L”, the data in the next address, which is
incremented, is over written.
CSN
CCLK
01 234 56 789
Clock, ‘H’ or ‘L’
14 15 0 1
67
01
67
Clock, ‘H’ or ‘L’
CDTI ‘H’ or ‘L’
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6
D1 D0 D7 D6
D1 D0
D7 D6
D1 D0 ‘H’ or ‘L’
Address: n
Data (Addr: n)
Data (Addr: n+1)
Data (Addr: n+N-1)
R/W:
A6-A0:
D7-D0:
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 56. Serial Control Interface Timing 2 (Continuous Writing Mode)
MS1343-E-00
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2011/12