AK4955 Datasheet, PDF (17/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
Parameter
Symbol
min
typ
max
Unit
Audio Interface Timing
Master Mode
BICK “↓” to LRCK Edge (Note 31)
LRCK Edge to SDTO (MSB)
(Except I²S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tMBLR
−40
-
tLRD
−70
-
tBSD
−70
-
tSDH
50
-
tSDS
50
-
40
ns
70
ns
70
ns
-
ns
-
ns
Slave Mode
LRCK Edge to BICK “↑” (Note 31)
BICK “↑” to LRCK Edge (Note 31)
LRCK Edge to SDTO (MSB)
(Except I²S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tLRB
50
-
tBLR
50
-
tLRD
-
-
tBSD
-
-
tSDH
50
-
tSDS
50
-
-
ns
-
ns
80
ns
80
ns
-
ns
-
ns
Control Interface Timing (3-wire Mode) (Note 32)
CCLK Period
tCCK
80
-
-
ns
CCLK Pulse Width Low
tCCKL
32
-
-
ns
Pulse Width High
tCCKH
32
-
-
ns
CDTIO Setup Time
tCDS
16
-
-
ns
CDTIO Hold Time
tCDH
16
-
-
ns
CSN “H” Time
tCSW
60
-
-
ns
CSN Edge to CCLK “↑” (Note 33)
tCSS
20
-
-
ns
CCLK “↑” to CSN Edge (Note 33)
tCSH
20
-
-
ns
CCLK “↓” to CDTIO (at Read Command)
tDCD
-
-
70
ns
CSN “↑” to CDTIO (Hi-Z) (at Read Command)(Note 35) tCCZ
-
-
70
ns
Control Interface Timing (I²C Bus Mode):
SCL Clock Frequency
fSCL
-
-
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
-
-
μs
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
-
-
μs
Clock Low Time
tLOW
1.3
-
-
μs
Clock High Time
tHIGH
0.6
-
-
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
-
μs
SDA Hold Time from SCL Falling (Note 36)
tHD:DAT
0
-
-
μs
SDA Setup Time from SCL Rising
tSU:DAT 0.1
-
-
μs
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
-
-
μs
Capacitive Load on Bus
Cb
-
-
400
pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
-
50
ns
Note 31. BICK rising edge must not occur at the same time as LRCK edge.
Note 32. When accessing to CODEC registers, the maximum frequency of CCLK for write operation is 12.5MHz and
6.75MHz for read operation, regardless of the operating frequency of the internal DSP. When accessing to the
DSP, CCLK and CDTI interface timings are changed depending on the operating frequency of the internal DSP.
For example, the DSP operating frequency (256times of the sampling frequency) is 12.288MHz, CCLK and
CDTI timings are multiplied by 12.5/12.288. (except tDCD and tCCZ) Then, the maximum frequency of CCLK
is 12.288MHz. (when DSP operating frequency = 12.288MHz)
Note 33. CCLK rising edge must not occur at the same time as CSN edge.
Note 34. I²C-bus is a trademark of NXP B.V.
Note 35. It is the time of 10% potential change of the CDTIO pin when R_L=1kΩ (pull-up to TVDD).
Note 36. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS1343-E-00
- 17 -
2011/12