AK4955 Datasheet, PDF (36/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
■ MIC Power
When PMMP bit = “1”, the MPWR pin supplies the power for microphones. This output voltage is typically 2.5V
@MICL bit =“0” (AVDD=2.9~3.6V), and typically 2.2V@MICL bit = “1” (AVDD=2.7V~3.6V). The load resistance is
minimum 0.5kΩ. In case of using two sets of stereo microphones, the load resistance is minimum 2kΩ for each channel.
Any capacitor must not be connected directly to the MPWR pin (Figure 29).
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 22. MIC Power
(default)
MIC Power
MPWR pin
LIN1 or LIN2
RIN1 or RIN2
Mi c ro phon e
Mi c ro phon e
Figure 29. MIC Block Circuit
■ Digital MIC
1. Connection to Digital Microphones
When DMIC bit is set to “1”, the LIN1 and RIN1 pins become DMDAT (digital microphone data input) and DMCLK
(digital microphone clock supply) pins, respectively. The same voltage as AVDD must be provided to the digital
microphone. The Figure 30 and Figure 31 show stereo/mono connection examples. The DMCLK clock is input to a
digital microphone from the AK4955. The digital microphone outputs 1bit data, which is generated by ΔΣModulator
using DMCLK clock, to the DMDAT pin. PMDML/R bits control power up/down of the digital block (Decimation Filter
and Digital Filter). (PMADL/PMADR bits settings do not affect the digital microphone power management. Set PMMP =
PMMICL/R bits to “0” when using a digital microphone.) The DCLKE bit controls ON/OFF of the output clock from the
DMCLK pin. When the AK4955 is powered down (PDN pin= “L”), the DMCLK and DMDAT pins become floating
state. Pull-down resistors must be connected to DMCLK and DMDAT pins externally to avoid this floating state.
MS1343-E-00
- 36 -
2011/12