AK4955 Datasheet, PDF (102/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
2. PLL Slave Mode (BICK pin)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D0)
BICK pin
Internal Clock
(1)
(2) (3)
1.0mses(max)
Input
(4)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 48kHz
4f₍s₁o₎ f_{Power Supply & PDN pin = “L” Æ “H”}
(2) Dummy command
Addr:05H, Data:32H
Addr:06H, Data:02H
(3) Addr:00H, Data:40H
(5)
Figure 79. Clock Set Up Sequence (2)
(4) Addr:01H, Data:01H
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 180ns or more is needed to reset the AK4955.
(2) After Dummy Command input, DIF1-0, PLL3-0, and FS3-0 bits must be set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is 0.4ms (typ)
and 1.0ms (max) when both capacitances of an external capacitor for the VCOM and REGFIL pins are 2.2μF.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK pin) is supplied. PLL
lock time is 2ms (max) when BICK is a PLL reference clock.
(5) Normal operation stats after that the PLL is locked.
MS1343-E-00
- 102 -
2011/12