AK4955 Datasheet, PDF (80/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
■ DSP Power-up Sequence
Set DSPSTBN bit to “1” to supply clock to the DSP after clock is stabilized (PLL lock). Program downloadings to the
DSP become available by setting DSPSTBN bit “0” → “1”. (There is no time limit for DSP program download.) Write a
program to PRAM and data to CRAM. The DSP is powered-up and DRAM initialization is started by PMDSP bit “0” →
“1”, after downloading a program.
DSPSTBN bit
PMPBP bit
DRAM Clear
DSP Start
DSP Program
Downloading Period
Initial power-up sequence wad abbreviated.
DRAM Clear
(230μs @ DSPC bit = “0”
fs = 48kHz)
DSP Program
Operation Start
Figure 74. DSP Power-up Sequence
In the DRAM clear sequence, it is possible to send commands to the DSP. (DSP is stopped during DRAM clear sequence.
The sent CRAM write command is accepted automatically after this sequence is completed.)
Initialization period of the DRAM is dependent on DSPC bit setting and sampling frequency.
Maximum 6LRCK≈125μsec@48kHz when DSPC bit= “1” (when DSP=512fs).
Maximum 11LRCK≈230μsec@48kHz when DSPC bit= “0” (when DSP=256fs).
MS1343-E-00
- 80 -
2011/12