AK4955 Datasheet, PDF (32/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
■ System Reset
Upon power-up, the AK4955 must be reset by bringing the PDN pin = “L”. This reset is released when a dummy
command is input after the PDN pin = “H”. This ensures that all internal registers reset to their initial value. Dummy
command is executed by writing all “0” to the register address 00H. It is recommended to set the PDN pin to “L” before
power up the AK4955.
CSN
CCLK _{“H” or “L”}
0 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
“H” or “L”
CDTIO “H” or “L”
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
R/W: READ/WRITE (“1”: WRITE)
A6-A0: Register Address (00H)
D7-D0: Control data (Input), (00H)
Figure 23. Dummy Command in 3-wire Serial Mode
S
T
A
R/W ="0"
R
T
Slave
SDA ^S Address
Sub
Address(00H)
S
T
O
P
Data(00H)
P
N
N
N
A
A
A
C
C
C
K
K
K
Figure 24. Dummy Command in I²C-bus Mode
The ADC starts an initialization cycle if the one of PMADL or PMADR is set to “1” when both of the PMADL and
PMADR bits are “0”. The initialization cycle is set by ADRST1-0 bits (Table 16). During the initialization cycle, the
ADC digital data outputs of both channels are forced to “0” in 2's complement. The ADC output reflects the analog input
signal after the initialization cycle is finished. When using a digital microphone, the initialization cycle is the same as
ADC’s.
(Note) The initial data of ADC has offset data that depends on microphones and the cut-off frequency of HPF. If this
offset is not small, make initialization cycle longer by setting ADRST1-0 bits or do not use the first data of ADC
outputs.
ADRST1-0 bits
00
01
10
11
Cycle
1059/fs
267/fs
531/fs
135/fs
Init Cycle
fs = 8kHz
fs = 16kHz
132.4ms
66.2ms
33.4ms
16.7ms
66.4ms
33.2ms
16.9ms
8.4ms
Table 16. ADC Initialization Cycle
fs = 48kHz
22ms
5.6ms
11.1ms
2.8ms
(default)
MS1343-E-00
- 32 -
2011/12