AK4955 Datasheet, PDF (106/117 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP/ LDO & DSP

[AK4955]
■ DSP Block
PLL mode
max .10ms
FS3-0 bits
(Addr: 06H, D3-0)
DSPSTBN bit
(Addr: 01H, D6)
0000
PMDSP bit
(Addr: 00H, D5)
DSP start
XXXX
(1)
(2)
(3)
DSP Program
Download Period
DRAM Initialization Cycle
(230μs @ DSPC bit =“0”
125μs @ DSPC bit =“1”)
DSP Program
Operation Start
Example
PLL mode
Sampling Frequency: 48kHz
(1) Addr: 06H, D3-0: Data: 0BH
(2) Addr: 01H, D7: DSPSTABN bit = “1”
(3) Addr: 1DH, D7: PMDSP bit = “1”
RAM Clear Period
DSP program Start
Figure 83. DSP Sequence
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) In PLL mode, access the DSP with an interval of PLL lock time (max. 10ms) after changing the sampling
frequency.
(2) Start program download period (Addr = 01H, D6 DSPSTBN bit = “1”). Write a program to PRAM and data to
CRAM during this period. There is no limit for the program download period.
(3) Power-up the DSP (Addr = 00H, D5 PMDSP bit = “1”). DRAM initialization starts when power-up the DSP
after downloading a program. DRAM initialization cycle is set by DSPC bit; max. 11LRCK≈230μs when
DSPC bit = “0” (DSP: 256fs operation) and max. 6LRCK≈125μs when DSPC bit = “1” (DSP: 512fs
operation).
MS1343-E-00
- 106 -
2011/12