AK4683_07 Datasheet, PDF (73/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
■ Register Map (DIR/DIT part)
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
00H CLK & Power Down Control CS12
1
CM1 CM0 OCKS1 OCKS0 PWN
01H Format & De-em Control
0
1
1
0
DEAU DEM1 DEM0
02H Input/ Output Control 0
TXE
0
OPS1 OPS0
0
0
0
03H Input/ Output Control 1
EFH1 EFH0
0
0
DIT
0
IPS1
04H INT MASK
MQIT0 MAUT0 MCIT0 MULK0 MDTS0 MPE0 MAUD0
05H TEST
1
0
1
1
0
1
0
06H Receiver status 0
QINT AUTO CINT UNLCK DTSCD PEM AUDION
07H Receiver status 1
FS3 FS2
FS1
FS0
0
V
QCRC
08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2
CR1
09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9
0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17
0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25
0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33
0DH TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2
CT1
0EH TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10
CT9
0FH TX Channel Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17
10H TX Channel Status Byte 3 CT31 CT30 CT29 CT28 CT27 CT26 CT25
11H TX Channel Status Byte 4 CT39 CT39 CT39 CT39 CT39 CT39 CT39
12H Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2
PC1
13H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10
PC9
14H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2
PD1
15H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10
PD9
16H Q-subcode Address / Control Q9
Q8
Q7
Q6
Q5
Q4
Q3
17H Q-subcode Track
Q17 Q16 Q15 Q14 Q13 Q12
Q11
18H Q-subcode Index
Q25 Q24 Q23 Q22 Q21 Q20
Q19
19H Q-subcode Minute
Q33 Q32 Q31 Q30 Q29 Q28
Q27
1AH Q-subcode Second
Q41 Q40 Q39 Q38 Q37 Q36
Q35
1BH Q-subcode Frame
Q49 Q48 Q47 Q46 Q45 Q44
Q43
1CH Q-subcode Zero
Q57 Q56 Q55 Q54 Q53 Q52
Q51
1DH Q-subcode ABS Minute
Q65 Q64 Q63 Q62 Q61 Q60
Q59
1EH Q-subcode ABS Second
Q73 Q72 Q71 Q70 Q69 Q68
Q67
1FH Q-subcode ABS Frame
Q81 Q80 Q79 Q78 Q77 Q76
Q75
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
The “0” register should be written “0”, the “1” register should be written “1” data.
D0
RSTN2
DFS
0
IPS0
MPAR0
1
PAR
CCRC
CR0
CR8
CR16
CR24
CR32
CT0
CT8
CT16
CT24
CT32
PC0
PC8
PD0
PD8
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
MS0427-E-02
- 73 -
2007/04