AK4683_07 Datasheet, PDF (61/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
(2). I²C bus control mode (I2C pin = “H”)
AK4683 supports the standard-mode I²C-bus (max: 100kHz). Then AK4683 does not support a fast-mode I²C-bus
system (max: 400kHz).
(2)-1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4683 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave
device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition
generated by the master device.
(2)-1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 41. Data transfer
(2)-1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 42. START and STOP conditions
MS0427-E-02
- 61 -
2007/04