AK4683_07 Datasheet, PDF (25/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
OPERATION OVERVIEW (ADC/DAC/PORTA, B part)
■ System Clock
The AK4683 has two audio serial interface (PORTA, B), can operate these PORTs with asynchronous. At each PORT,
the external clocks, which are required to operate the AK4683, are MCLK, LRCK and BICK. The MCLK should be
synchronized with LRCK but the phase is not critical.
The CLKA1-0, CLKB1-0bits select the clock sources for each PORT (Table 8, Table 9). The MSA and MSB bits select
the master/slave mode (Table 16, Table 17).
The block that is connected to PORTA/B and the block that is connected to the PORT indirectly operate at the same
clock as the PORTA/B selects. e. g. When the DAC selects the ADC data while the PORTB selects the ADC data also,
the DAC operates same clock as the PORTB selects. The block that isn’t connected to PORTA/B is automatically
connected to the Clock Gen C and operates the same clock as the Clock Gen C selects with the CLKL1-0 bits (Table
10).
In master mode, the CKSIA2-0, OLRA1-0, BICKAF, CKSB2-0 bits select the clock frequency (Table 11, Table 12 ,
Table 13, Table 14). In master mode, external clock (MCLK) should always be supplied except in the power-down
mode. The AK4683 is in power-down mode until MCLK will be supplied, when reset was canceled by Power-ON and
so on. At PORTA, the input/output data has independent LRCK (ILRCKA/OLRCKA) and common BICK (BICKA).
The ILRCK and OLRCK can operate at different sample rate but synchronized each other (Table 12).
In slave mode, external clocks (MCLK, BICK, LRCK) should always be present whenever the AK4683 is in normal
operation mode (PDN pin = “H”). The master clock (MCLK) should be synchronized with LRCK but the phase is not
critical. If these clocks are not provided, the AK4683 may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the AK4683 should be in the power-down mode (PDN
pin = “L”) or in the reset mode (RSTN1 bit = “0”). After exiting reset at power-up etc., the AK4683 is in the
power-down mode until MCLK and LRCK are input.
When the block selects RMCLK as clock source, the sample rate of the PORT in the master mode or ADC/DAC
connecting to the Clock Gen C is forced to the same rate as DIR. The DFSAD, DFSDA1-0 bits should be controlled
properly.
Note: When PORTA and PORTB operate synchronously, PORTB must not be the in Master Mode. In that case
the PORTA must be in the Master Mode, or both PORTA and PORTB must be in the Slave Mode with
supplying the same BICK and LRCK.
MS0427-E-02
- 25 -
2007/04