AK4683_07 Datasheet, PDF (43/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
■ Status of analog output pins during power-down (PDN pin =”L”)
The status of analog output pins is as follows.
Pin Name
HPL/HPR
LOUT1/ROUT1/LOUT2/ROUT2
LISEL/RISEL
HVSS
VCOM
Hi-Z
■ Reset Function
When RSTN1 bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog
outputs go to VCOM voltage, DZF/OVF pin goes to “H” and SDTOA/B pins go to “L”. Because some click noise
occurs, the analog output should be muted externally if the click noise influences system application. The Figure 24
shows the power-up sequence.
RSTN bit
Internal
RSTN bit
ADC Internal
State
Normal Operation
4~5/fs (9)
1~2/fs (9)
Digital Block Power-down
516/fs ⁽¹⁾
Init Cycle
Normal Operation
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
Normal Operation
Digital Block Power-down
GD ⁽²⁾
(3)
“0”data
Normal Operation
GD
(4)
DAC In
(Digital)
“0”data
(2)
GD
GD
DAC Out
(Analog)
(6) (5)
(6)
Clock In
MCLK,LRCK,SCLK
(7)
Don’t care
DZF1/DZF2
4∼5/fs (8)
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application.
(5) When RSTN1 bit = “0”, the analog outputs go to VCOM voltage.
(6) Click noise occurs at 4∼5/fs after RSTN1 bit becomes “0”, and occurs at 1∼2/fs after RSTN1 bit becomes “1”.
This noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICKA (BICKB), LRCKA (LRCKB)) can be stopped in the reset mode. When
exiting the reset mode, “1” should be written to RSTN1 bit after the external clocks (MCLK, BICKA (BICKB),
LRCKA (LRCKB)) are fed.
(8) DZF pins go to “H” when the RSTN1 bit becomes “0”, and go to “L” at 6~7/fs after RSTN1 bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN1 bit “0” to the internal RSTN bit “0”.
Figure 24. Reset sequence example
MS0427-E-02
- 43 -
2007/04