AK4683_07 Datasheet, PDF (68/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
Addr
03H
Register Name
Clock Select 2
Default
D7
CKSL2
0
D6
CKSL1
1
D5
CKSL0
0
D4
CLKL1
0
D3
CLKL0
1
D2
MCKO1
0
D1
MCKO0
1
D0
CLKDT
0
CLKDT: Clock source control for DIT
Refer Table 56.
MCLKO1-0: Clock source control for MCLKO
Refer Table 4.
CLKL1-0: Clock source control for Clock Gen C
00: DIR
01: X’tal(XTI) (default)
10: MCLK2
11: (Reserved)
CLSL2-0: Clock control for Clock Gen C
Refer Table 15
Addr
04H
Register Name
Clock Select 3
Default
D7
CKSAI2
0
D6
CKSAI1
1
D5
CKSAI0
0
D4
SELAO
0
D3
OLRA1
0
D2
OLRA0
0
D1
BCAF
0
D0
MSA
0
MSA: Master/Slave control for input data of PORTA.
Refer Table 16.
BCAF: Bit clock control for PORTA
Refer Table 13.
OLRA1-0: Clock control for PORTA OLRCKA.
Refer Table 12.
SELAO: Clock control for DIR/DIT
0: Except for the case at “1”. (default)
1: Selects when the frequency of ILRCKA and OLRCKA are different, DITD[1:0]= “00” or “01”
and both SDTOA[1:0] and DITD[1:0] select same data source.
CKSAI2-0: Clock control for PORTA Input Data.
Refer Table 11.
MS0427-E-02
- 68 -
2007/04