AK4683_07 Datasheet, PDF (46/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
OPERATION OVERVIEW (DIR/DIT part)
■ 192kHz Clock Recovery
On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4683
has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel
status, the AK4683 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz).
The PLL loses lock when the received sync interval is incorrect.
■ Clock Operation Mode
When DIR is selected. the CM0/CM1 bits select the clock source and the data source of SDTO. In Mode 2, the clock
source is automatically switched from PLL to XTI/MCLK2 when PLL goes unlock state. In Mode 3, the clock source is
fixed to XTI/MCLK2, but PLL is also operating and the recovered data such as C bits can be monitored. For Mode 2
and 3, it is recommended that the frequency of XTI/MCLK2 is different from the recovered frequency from PLL.
Mode
0
1
2
3
CM1
0
0
1
1
CM0 UNLOCK PLL Clock source SDTO
0
-
ON
PLL
RX
1
-
OFF EXTCLK DIT source
0
0
ON
PLL
RX
1
ON
EXTCLK DIT source
1
-
ON
EXTCLK DIT source
ON: Oscillation (Power-up), OFF: STOP (Power-down)
(default)
Table 45. Clock Operation Mode select
When 384fs of XTI/MCLK2 is supplied to DIR/DIT, CKSDT bit should be set to “1”.
CKSDT bit
0
1
Clock Speed
x1
x 2/3
(default)
Table 46. XTI/MCLK2 speed
MS0427-E-02
- 46 -
2007/04