AK4683_07 Datasheet, PDF (30/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
LRCKA
(LRCKB)
Fs
176.4kHz
192.0kHz
MCLK (MHz)
BICKA (BICKB)
(MHz)
128fs
192fs
256fs
64fs
22.5792
-
-
11.2896
24.5760
-
-
12.2880
(Quad Speed Mode @Manual Setting Mode)
(Note: ADC is not available at the Quad Speed Mode)
Table 25. System clock example
2. Auto Setting Mode (ACSKAD/ACSKDA bit = “1”)
When the ADC and DACs are connected to each PORT placed in Auto Setting Mode, MCLK frequency is detected
automatically (Table 26) and the internal master clock is set to the appropriate frequency (Table 27). In this mode, the
setting of DFSAD, DFSDA1-0 bits are ignored.
MCLK
512fs
256fs
128fs
Sampling Speed
Normal
Double
Quad
Table 26. Sampling Speed (Auto Setting Mode)
LRCKA
(LRCKB)
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
128fs
-
-
-
-
-
22.5792
24.5760
256fs
-
-
-
22.5792
24.5760
-
-
512fs
16.3840
22.5792
24.5760
-
-
-
-
Sampling
Speed
Normal
Double
Quad
Table 27. System clock example (Auto Setting Mode)
MS0427-E-02
- 30 -
2007/04