AK4683_07 Datasheet, PDF (65/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
■ Register Map (ADC/DAC part)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Powerdown 1
Powerdown 2
Clock Select 1
Clock Select 2
Clock Select 3
Clock Select 4
Sampling Speed
Data Source Select 1
Data Source Select 2
Analog Input Control
Audio Data Format
De-emphasis/ ATT speed
LIN Volume Control
RIN Volume Control
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
HPL Volume Control
OVF/DZF/V Control
D7
PWXTL
PWPOB
0
CKSL2
CKSAI2
0
0
0
0
0
0
DEM11
ATTAD7
ATTAD7
ATTDA7
ATTDA7
ATTDA7
ATTDA7
0
0
D6
MUTEN
PWPOA
0
CKSL1
CKSAI1
XTL1
ACKSAI
0
DAC22
0
0
DEM10
ATTAD6
ATTAD6
ATTDA6
ATTDA6
ATTDA6
ATTDA6
0
0
D5
PWVR
PWDA
0
CKSL0
CKSAI0
XTL0
ACKSAO
DITD1
DAC21
0
DIFB1
DEM21
ATTAD5
ATTAD5
ATTDA5
ATTDA5
ATTDA5
ATTDA5
0
ZCE
D4
PWHP
PWAD
0
CLKL1
0
CKSDT
ACKSB
DITD0
DAC20
0
DIFB0
DEM20
ATTAD4
ATTAD4
ATTDA4
ATTDA4
ATTDA4
ATTDA4
OPGA4
VIN
D3
0
0
CLKB1
CLKL0
OLRA1
CKSB2
0
SDTOB1
0
0
TDMA1
0
ATTAD3
ATTAD3
ATTDA3
ATTDA3
ATTDA3
ATTDA3
OPGA3
FUNC1
D2
SMAD
0
CLKB0
MCKO1
OLRA0
CKSB1
DFSAD
SDTOB0
DAC12
AIN2
TDMA0
ATSAD
ATTAD2
ATTAD2
ATTDA2
ATTDA2
ATTDA2
ATTDA2
OPGA2
FUNC0
D1
SMDA
PWDA2
CLKA1
MCKO0
BCAF
CKSB0
DFSDA1
SDTOA1
DAC11
AIN1
DIFA1
0
ATTAD1
ATTAD1
ATTDA1
ATTDA1
ATTDA1
ATTDA1
OPGA1
DZFM1
D0
RSTN1
PWDA1
CLKA0
CLKDT
MSA
MSB
DFSDA0
SDTOA0
DAC10
AIN0
DIFA0
ATSDA
ATTAD0
ATTAD0
ATTDA0
ATTDA0
ATTDA0
ATTDA0
OPGA0
DZFM0
Note: For addresses from14H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN1 bit goes to “0”, the internal timing is reset and DZF pin goes to “H”, but registers are not initialized
to their default values.
MS0427-E-02
- 65 -
2007/04