AK4683_07 Datasheet, PDF (20/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
OPERATION OVERVIEW (General)
■ Device Configuration and System Clocks
The AK4683 integrates the stereo ADC with input selector, 4ch DAC with stereo HP amp, DIR and DIT. The AK4683
has two serial audio interfaces (PORTA, B) for two input/output dataset (Figure 2). Each block can independently select
the operation clock from the three clock sources (recovered clock from DIR (RMCLK), X’tal clock (XTI) and external
clock (MCLK2)) and also input data source/output data destination. By using the Clock Gen C, the loop-back such as
AD-DA can operate even if the PORTA/B are powered down.
DIR
X’tal
Oscillator
(XTI)
MCLK2
DIR
XTI
MCLK2
MCKO0/1 bit
DIR
XTI
MCLK2
CLKB0/1 bit
DIR
XTI
MCLK2
CLKA0/1 bit
DIR
XTI
MCLK2
CLKL0/1 bit
MCKO
PORTA
Clock
Gen A
PORTB
Clock
Gen B
Clock
Gen C
Note
DIR
XTI
MCLK2
DIR
XTI
MCLK2
DIR
XTI
MCLK2
ADC
DAC
DIT
Figure 2 System Clock
Note: Each block must select the same clock source each other when connected. The operation will not be normal when
the clock sources are not same among a connection. The ADC and DAC are synchronized to the clock source that
the connected block uses. Even if the RMCLK is selected, the X’tal/MCLK2 may be chosen by the setting of
CM1-0bits. DIR and DIT must be synchronized when these two blocks operates.
MS0427-E-02
- 20 -
2007/04