AK4683_07 Datasheet, PDF (27/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
BCAF bit
PORTA BICK Frequency Mode
0
ILRCK x 64
(default)
1
ILRCK x128
Note: ILRCK x 128 is available when the MCLK=ILRCK x 256 or higher.
BCAF bit is ignored in TDM mode.
Table 13. PORTA BICK Control (Master Mode)
CKSB2
0
0
0
0
1
1
1
1
CKSB1
0
0
1
1
0
0
1
1
CKSB0
0
1
0
1
0
1
0
1
Clock Speed
128fs
192fs
256fs
384fs
512fs
Reserved
Reserved
Reserved
(default)
Table 14. PORTB Data Clock Control (Master Mode)
CKSL2
0
0
0
0
1
1
1
1
CKSL1
0
0
1
1
0
0
1
1
CKSL0
0
1
0
1
0
1
0
1
Clock Speed
128fs
192fs
256fs
384fs
512fs
Reserved
Reserved
Reserved
Table 15. Clock Gen C Clock Control
(default)
In master mode, LRCKA (LRCKB) pin, BICKA (BICKB) pin are output pins. In slave mode, these are input pins
(Table 18).
MSA bit
0
1
PORTA Master/Slave Mode
Slave
Master
(default)
Table 16. PORTA Master/Slave Control
MSB bit
0
1
PORTB Master/Slave Mode
Slave
Master
Table 17. PORTB Master/Slave Control
(default)
MS0427-E-02
- 27 -
2007/04