AK4683_07 Datasheet, PDF (14/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
Parameter
Symbol
min
typ
Control Interface Timing (4-wire serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I²C Bus mode)
tCSS
50
tCSH
50
tDCD
tCCZ
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
4.7
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 4.0
Clock Low Time
tLOW
4.7
Clock High Time
tHIGH
4.0
Setup Time for Repeated Start Condition
tSU:STA
4.7
SDA Hold Time from SCL Falling
(Note 27)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.25
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
4.0
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Capacitive load on bus
Cb
-
Note 27. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 28. I²C is a registered trademark of Philips Semiconductors.
max Units
ns
ns
ns
ns
ns
ns
ns
ns
45
ns
70
ns
100 kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
1.0
μs
0.3
μs
-
μs
50
ns
400
pF
MS0427-E-02
- 14 -
2007/04