AK4683_07 Datasheet, PDF (48/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
■ De-emphasis Filter Control
The AK4683 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to four sampling
frequencies (32kHz, 44.1kHz, 48kHz and 96kHz). When DEAU bit=“1”, the de-emphasis filter is enabled automatically
by sampling frequency and pre-emphasis information in the channel status. The AK4683 goes this mode at default.
Therefore, in Parallel Mode, the AK4683 is always placed in this mode and the status bits in channel 1 control the
de-emphasis filter. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU bit is “0”. The
internal de-emphasis filter is bypassed and the recovered data is output without any change if either pre-emphasis or
de-emphasis Mode is OFF.
PEM
FS3
FS2
FS1
FS0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
1
1
1
0
1
0
1
(Others)
0
x
x
x
x
Mode
44.1kHz
48kHz
32kHz
96kHz
OFF
OFF
Table 51. De-emphasis Auto Control at DEAU bit = “1” (default)
PEM
1
1
1
1
1
1
1
1
0
DFS
DEM1
DEM0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
x
x
x
Mode
44.1kHz
OFF
48kHz
32kHz
OFF
OFF
96kHz
OFF
OFF
(default)
Table 52. De-emphasis Manual Control at DEAU bit = “0”
■ System Reset and Power-Down
The AK4683 has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The
RSTN2 bit initializes the register and resets the internal timing. The AK4683 should be reset once by bringing PDN pin
= “L” upon power-up.
PDN pin: All analog and digital circuit are placed in the power-down and reset mode by bringing PDN pin = “L”. All
the registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled.
RSTN2 bit: All the registers except PWN and RSTN2 bits are initialized by bringing RSTN2 bit = “0”. The internal
timings are also initialized. When RSTN2 bit = “0”, the clock are output but SDTO pin is hold to “L”.
Witting to the register is not available except PWN and RSTN2 bits. Reading to the register is disabled.
PWN bit: The clock recovery part is initialized by bringing PWN bit = “0”. In this case, clocks from PLL are stopped.
The registers are not initialized and the mode settings are kept. Writing and Reading to the registers are
enabled.
MS0427-E-02
- 48 -
2007/04