AK4683_07 Datasheet, PDF (22/84 Pages) Asahi Kasei Microsystems – Asynchronous Multi-Channel Audio CODEC with DIR/T

[AK4683]
■ Master Clock Output
The AK4683 has one master clock output pin. The clock source can be selected from the three clocks (recovered clock
from DIR (RMCLK), X’tal clock (XTI) and external clock (MCLK2)). When the DIR is powered-down or unlocked
state at CM1/0 bit = “10”, the CLKDT bit selects the clock source. The OCKS1/0 bits select the clock speed. The 512fs
at fs=96kHz, 256fs/512fs at fs=192kHz are not available.
CM1 bit
0
0
1
1
CM0 bit
0
1
0
1
UNLOCK
-
-
0
1
-
Clock Source
RMCLK
EXTCLK
RMCLK
EXTCLK
EXTCLK
Table 1. Clock Mode Control
CLKDT bit
0
1
Clock Source
XTI
MCLK2
Default
Table 2. EXTCLK Control
OCKS1 bit
0
0
1
1
OCKS0 bit
0
1
0
1
MCLKO(RMCLK)
256fs
256fs
512fs
128fs
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Table 3. MCLKO Speed
MCKO1 bit
0
0
1
1
MCKO0 bit
0
1
0
1
MCKO Clock Source
DIR
X’tal(XTI)
MCLK2
Reserved
default
Table 4. MCKO Clock Source Control
OCKS1/0 bit
PLL
RMCLK
X’tal
Oscillator
(XTI)
MCLK2
CLKDT bit
EXTCLK
x2/3
CM0/1 bit
CKSDT bit
DIR
XTI
MCLK2
MCKO
MCKO0/1 bit
Figure 7. MCKO Clock
MS0427-E-02
- 22 -
2007/04