Z8F1601 Datasheet, PDF (73/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!^®
55
Interrupt Port Select register selects between Port A and Port D for the individual inter-
rupts.
Table 35. Interrupt Edge Select Register (IRQES)
BITS
7
6
5
4
3
2
1
0
FIELD ^IES7
IES6
IES5
IES4
IES3
IES2
IES1
IES0
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FCDH
IESx—Interrupt Edge Select x
where x indicates the specific GPIO Port pin number (0 through 7). The pulse width
should be greater than 1 system clock to guarantee capture of the edge triggered interrupt.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
Interrupt Port Select Register
The Port Select (IRQPS) register (Table 36) determines the port pin that generates the
PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as inter-
rupts. The Interrupt Edge Select register controls the active interrupt edge.
Table 36. Interrupt Port Select Register (IRQPS)
BITS
FIELD
RESET
R/W
ADDR
7
PAD7S
0
R/W
6
PAD6S
0
R/W
5
PAD5S
0
R/W
4
PAD4S
3
PAD3S
0
0
R/W
R/W
FCEH
2
PAD2S
0
R/W
1
PAD1S
0
R/W
PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
where x indicates the specific GPIO Port pin number (0 through 7).
0
PAD0S
0
R/W
PS017610-0404
Interrupt Controller