Z8F1601 Datasheet, PDF (121/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!^®
103
Transfer Format PHASE Equals Zero
Figure 77 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to
0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set
to one. The diagram may be interpreted as either a Master or Slave timing diagram since
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MISO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Input Sample Time
SS
Figure 77. SPI Timing When PHASE is 0
Transfer Format PHASE Equals One
Figure 78 illustrates the timing diagram for an SPI transfer in which PHASE is one. Two
waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for CLKPOL set
to 1.
PS017610-0404
Serial Peripheral Interface