Z8F1601 Datasheet, PDF (12/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!^®
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List of Tables
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Z8F640x Family Part Selection Guide . . . . . . . . . . . . . . . . 2
Z8F640x Family Package Options . . . . . . . . . . . . . . . . . . . 6
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Characteristics of the Z8F640x family . . . . . . . . . . . . 15
Z8F640x Family Program Memory Maps . . . . . . . . . . . . . 18
Z8F640x Family Data Memory Maps . . . . . . . . . . . . . . . . 19
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset and STOP Mode Recovery Characteristics
and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . 26
STOP Mode Recovery Sources and Resulting Action . . . 29
Port Availability by Device and Package Type . . . . . . . . . 33
Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . 35
Port A-H GPIO Address Registers (PxADDR) . . . . . . . . . 37
GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . 37
Port A-H Control Registers (PxCTL) . . . . . . . . . . . . . . . . 38
Port A-H Data Direction Sub-Registers . . . . . . . . . . . . . . . 39
Port A-H Alternate Function Sub-Registers . . . . . . . . . . . 39
Port A-H Output Control Sub-Registers . . . . . . . . . . . . . . 40
Port A-H High Drive Enable Sub-Registers . . . . . . . . . . . 41
Port A-H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . 42
Port A-H STOP Mode Recovery Source Enable
Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port A-H Output Data Register (PxOUT) . . . . . . . . . . . . . 43
Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . 45
Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . 48
Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . 49
Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . 50
IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . 51
IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . 51
IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . 52
IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . 52
IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . 53
PS017610-0404
List of Tables