Z8F1601 Datasheet, PDF (130/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!^®
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limit to the amount of data transferred in one operation. When transmitting data or
acknowledging read data from the slave, the SDA signal changes in the middle of the low
period of SCL and is sampled in the middle of the high period of SCL.
I²C Interrupts
the I²C Controller contains three sources of interrupts—Transmit, Receive and Not
Acknowledge (NAK) interrupts. NAK interrupts occur when a Not Acknowledge is
received from the slave or sent by the I²C Controller and the Start or Stop bit is set. This
source sets bit 0 and can only be cleared by setting the Start or Stop bit. When this inter-
rupt occurs, the I²C Controller waits until it is cleared before performing any action. In an
interrupt service routine, this interrupt must be the first thing polled. Receive interrupts
occur when a byte of data has been received by the I²C master. This interrupt is cleared by
reading from the I²C Data register. If no action is taken, the I²C Controller waits until this
interrupt is cleared before performing any other action.
For Transmit interrupts to occur, the TXI bit must be 1 in the I²C Control register. Trans-
mit interrupts occur under the following conditions when the transmit data register is
empty:
• The I²C Controller is idle (not performing an operation).
• The START bit is set and there is no valid data in the I²C Shift or I²C Data register to
shift out.
• The first bit of the byte of an address is shifting out and the RD bit of the I²C Status
register is deasserted.
• The first bit of a 10-bit address shifts out.
• The first bit of write data shifted out.
Note: Writing to the I²C Data register always clears a Transmit interrupt.
Start and Stop Conditions
The master (I²C) drives all Start and Stop signals and initiates all transactions. To start a
transaction, the I²C Controller generates a START condition by pulling the SDA signal
low while SCL is high. Then a high-to-low transition occurs on the SDA signal while the
clock is High. To complete a transaction, the I²C Controller generates a Stop condition by
creating a low-to-high transition of the SDA signal in the middle of the high period of the
SCL signal.When the SCL signal is High, the master generates a Start bit by pulling a
High SDA signal Low and generates a Stop bit by releasing the SDA signal. The Start and
Stop signals are found in the I²C Control register and must be written by software when
the Z8F640x family device must begin or end a transaction.
Writing a Transaction with a 7-Bit Address
1. The I²C Controller shifts the I²C Shift register out onto SDA signal.
PS017609-0803
I2C Controller