Z8F1601 Datasheet, PDF (70/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!^®
52
Table 28. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
FIELD
RESET
R/W
ADDR
7
T2ENL
0
R/W
6
T1ENL
0
R/W
5
T0ENL
0
R/W
4
3
U0RENL U0TENL
0
0
R/W
R/W
FC2H
2
I2CENL
0
R/W
1
0
SPIENL ADCENL
0
0
R/W
R/W
T2ENL—Timer 2 Interrupt Request Enable Low Bit
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I²C Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers (Tables 30 and 31) form a priority encoded
enabling for interrupts in the Interrupt Request 1 register. Priority is generated by setting
bits in each register. Table 29 describes the priority control for IRQ1.
Table 29. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
where x indicates the register bits from 0 through 7.
PS017610-0404
Interrupt Controller