Z8F1601 Datasheet, PDF (197/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
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SPI Master Mode Timing
Figure 96 and Table 110 provide timing information for SPI Master mode pins. Timing is
shown with SCK rising edge used to source MOSI output data, SCK falling edge used to
sample MISO input data. Timing on the SS output pin(s) is controlled by software.
SCK
T1
MOSI
(Output)
MISO
(Input)
Output Data
T2 T3
Input Data
Figure 96. SPI Master Mode Timing
Table 110. SPI Master Mode Timing
Parameter
T₁
T₂
T₃
Abbreviation
SCK Rise to MOSI output Valid Delay
MISO input to SCK (receive edge) Setup Time
MISO input to SCK (receive edge) Hold Time
Delay (ns)
Minimum Maximum
-5
+5
20
0
PS017610-0404
Electrical Characteristics