Z8F1601 Datasheet, PDF (14/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!^®
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Table 67. I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . 118
Table 68. I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . 118
Table 69. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . 119
Table 70. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . 121
Table 71. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . 121
Table 72. DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . 124
Table 73. DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . 126
Table 74. DMAx Address High Nibble Register (DMAxH) . . . . . . 126
Table 75. DMAx End Address Low Byte Register (DMAxEND) . 128
Table 76. DMAx Start/Current Address Low Byte Register
(DMAxSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 77. DMA_ADC Register File Address Example . . . . . . . . . . 129
Table 78. DMA_ADC Address Register (DMAA_ADDR) . . . . . . 129
Table 79. DMA_ADC Control Register (DMAACTL) . . . . . . . . . . 130
Table 80. DMA_ADC Status Register (DMAA_STAT) . . . . . . . . . 131
Table 81. ADC Control Register (ADCCTL) . . . . . . . . . . . . . . . . . 135
Table 82. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . 137
Table 83. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . 137
Table 84. Z8F640x family Flash Memory Configurations . . . . . . . 138
Table 85. Flash Code Protection Using the Option Bits . . . . . . . . . 142
Table 86. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . 144
Table 87. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . 145
Table 88. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . 146
Table 89. Flash Frequency High Byte Register (FFREQH) . . . . . . 147
Table 90. Flash Frequency Low Byte Register (FFREQL) . . . . . . . 147
Table 91. Option Bits At Program Memory Address 0000H . . . . . 149
Table 92. Options Bits at Program Memory Address 0001H . . . . . 150
Table 93. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 94. On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . 156
Table 95. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . 161
Table 96. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . 162
Table 97. OCD Watchpoint Control/Address (WPTCTL) . . . . . . . 163
Table 98. OCD Watchpoint Address (WPTADDR) . . . . . . . . . . . . 164
Table 99. OCD Watchpoint Data (WPTDATA) . . . . . . . . . . . . . . . 164
Table 100. Recommended Crystal Oscillator Specifications
(20MHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
PS017610-0404
List of Tables