Z8F1601 Datasheet, PDF (40/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!^®
22
Table 6. Register File Address Map (Continued)
Address (Hex)
F62
F63
F64-F65
F66
F67
F68-F69
Register Description
SPI Status
SPI Mode
Reserved
SPI Baud Rate High Byte
SPI Baud Rate Low Byte
Reserved
Analog-to-Digital Converter (ADC)
F70
ADC Control
F71
Reserved
F72
ADC Data High Byte
F73
ADC Data Low Bits
F74-FAF
Reserved
DMA 0
FB0
FB1
FB2
FB3
FB4
DMA0 Control
DMA0 I/O Address
DMA0 End/Start Address High Nibble
DMA0 Start Address Low Byte
DMA0 End Address Low Byte
DMA 1
FB8
FB9
FBA
FBB
FBC
DMA1 Control
DMA1 I/O Address
DMA1 End/Start Address High Nibble
DMA1 Start Address Low Byte
DMA1 End Address Low Byte
DMA ADC
FBD
FBE
FBF
DMA_ADC Address
DMA_ADC Control
DMA_ADC Status
Interrupt Controller
FC0
Interrupt Request 0
FC1
IRQ0 Enable High Bit
FC2
IRQ0 Enable Low Bit
FC3
Interrupt Request 1
FC4
IRQ1 Enable High Bit
FC5
IRQ1 Enable Low Bit
FC6
Interrupt Request 2
FC7
IRQ2 Enable High Bit
FC8
IRQ2 Enable Low Bit
FC9-FCC
Reserved
FCD
Interrupt Edge Select
XX=Undefined
Mnemonic
SPISTAT
SPIMODE
—
SPIBRH
SPIBRL
—
Reset (Hex)
01
00
XX
FF
FF
XX
Page #
108
109
110
110
ADCCTL
20
135
—
XX
ADCD_H
XX
137
ADCD_L
XX
137
—
XX
DMA0CTL 00
124
DMA0IO
XX
125
DMA0H
XX
126
DMA0START XX
127
DMA0END XX
128
DMA1CTL 00
124
DMA1IO
XX
125
DMA1H
XX
126
DMA1START XX
127
DMA1END XX
128
DMAA_ADDR XX
128
DMAACTL 00
130
DMAASTAT 00
131
IRQ0
00
48
IRQ0ENH 00
51
IRQ0ENL
00
51
IRQ1
00
49
IRQ1ENH 00
52
IRQ1ENL
00
52
IRQ2
00
50
IRQ2ENH 00
53
IRQ2ENL
00
53
—
XX
IRQES
00
54
PS017610-0404
Register File Address Map