Z8F1601 Datasheet, PDF (137/246 Pages) Zilog, Inc. – Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter

Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
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received a byte of data. When active, this bit causes the I²C Controller to generate an
interrupt. This bit is cleared by reading the I²C Data register.
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge was received for the last byte transmitted
or received.
10B—10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit
is set, if the five most-significant bits of the address are 11110B, this bit is set. When set,
it is reset once the first byte of the address has been sent.
RD—Read
This bit indicates the direction of transfer of the data. It is active high during a read. The
status of this bit is determined by the least-significant bit of the I²C Shift register after the
START bit is set.
TAS—Transmit Address State
This bit is active high while the address is being shifted out of the I²C Shift register.
DSS—Data Shift State
This bit is active high while data is being transmitted to or from the I²C Shift register.
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only
be cleared by setting the START or STOP bit, allowing the user to specify whether he
wants to perform a STOP or a repeated START.
I²C Control Register
The I²C Control register enables the I²C operation.
Table 68. I²C Control Register (I2CCTL)
BITS
7
FIELD ^IEN
RESET
0
R/W
R/W
ADDR
6
START
0
R/W
5
STOP
0
R/W
4
3
BIRQ
TXI
0
0
R/W
R/W
F52H
IEN—I²C Enable
This bit enables the I²C transmitter and receiver.
2
NAK
0
R/W
1
FLUSH
0
R/W
0
FILTEN
0
R/W
PS017609-0803
I2C Controller