DS626 Datasheet, PDF (9/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
Table 2: MCH_PLBv46_Slave_Burst Design Parameters (Cont’d)
Generic
Feature /
Description
Parameter Name Allowable Values
XCL Channels
Array indicating the
size of the cacheline
G11
in number of 32-bit
words for each
channel configured
C_XCL_LINESIZE
_ARRAY ⁽⁶⁾
with the XCL
protocol ⁽¹⁾
One entry for each
XCL channel.
Allowed entries:
1,4,8,16 for XCL
channels
Array indicating the
type of write
G12
transactions for each ^{C_XCL_WRITEXFER}
channel configured _{_ARRAY}⁽⁶⁾⁽⁷⁾
with the XCL
protocol
One entry for each
XCL channel.
Allowed entries:
0 = no write transfers
1 = single transfers
only
2 = cacheline
transfers only
PLB Interface
G13
Data width of plbv46
interfaces
C_SPLB_DWIDTH
32, 64, 128
G14
Selects point-to-
point bus topology
C_SPLB_P2P
0,1
0 = Target word first
G15
Cache Line
Addressing Mode
C_CACHLINE_ADDR_MO on reads.
DE
1 = Line word First
on reads
0, 16, 32, or 64
G16 Write Buffer Depth C_WR_BUFFER_DEPTH _{0 = no write buffer}
implemented
G17
Data width of the
smallest master
C_SPLB_SMALLEST_MA
STER
32, 64, 128
G18
Number of PLB
Masters
C_SPLB_NUM_MASTERS 1 - 16
G19
PLB Master ID Bus
width
C_SPLB_MID_WIDTH
0-4
Default
Value
{4}
{1}
32
0
0
16
1
1
VHDL
Type
integer
array
integer
array
integer
integer
integer
integer
integer
integer
integer
DS626 April 24, 2009
www.xilinx.com
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Product Specification