DS626 Datasheet, PDF (10/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
Table 2: MCH_PLBv46_Slave_Burst Design Parameters (Cont’d)
Generic
Feature /
Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
Array of Base
Address / High
G20
Address Pairs for
each Address
Range. The address
ranges in this array
correspond the to
Bus2IP_CS
C_PLB_ARD_ADDR_RAN
GE_ARRAY^{(8) (9)(10)}
See the PLBv46
Slave Burst V1_00_a
Product
Specification for
description.
User must
set values.
SLV64_AR
RAY_TYPE
generated from the
PLBv46 Slave Burst.
G21
Array of the desired
number of chip
enables for each
address space
C_PLB_ARD_NUM_CE_A
RRAY^{(8) (9)}
See the PLBv46
Slave Burst V1_00_a
Product
Specification for
description.
User must
set values.
integer
array
1. Only fixed arbitration is supported at this time.
2. Each channel can be configured to support a transfer protocol. Only the Xilinx Cachelink (XCL) protocol is sup-
ported at this time.
3. This array should only contain user IP address ranges which are accessible through the MCH interfaces. The
order of entries through this array should match the order of entries in C_PLB_ARD_ADDR_RANGE_ARRAY.
4. Best performance (higher F_MAX, lower latency) is achieved when there is only one user IP address range ac-
cessible through the MCH interfaces.
5. If the channel is connected to a master which can consume data as soon as it is available (i.e., instruction side
interfaces), set the depth of the read data buffer to zero for that channel to save resources and latency.
6. If C_MCH_CHANNEL_PROTOCOL(x) is not set to XCL, then entry x in these arrays is unused.
7. If the master connecting to channel x will only perform read transfers, (i.e., instruction cache masters), set entry
x in this array to 0.
8. The generics associated with the PLB Slave interface are unused when C_INCLUDE_PLB_IPIF=0.
9. The generics associated with the PLB Slave Interface are described in the PLBv46 Slave Burst Parameter De-
tailed Description section of the Xilinx LogiCORE DS424 PLBv46 Slave Burst v1.00.A Product Specification and
will not be described in this document.
10. User IP address ranges which are also accessible through MCH interfaces should be listed first in these arrays.
Allowable Parameter Combinations
The PLB slave interface is only included in this design if C_INCLUDE_PLB_IPIF is set to 1. When
C_INCLUDE_PLB_IPIF = 0, the generics associated with the PLB interface (C_SPLB_P2P,
C_CACHLINE_ADDR_MODE, C_WR_BUFFER_DEPTH, C_PLB_ARD_ADDR_RANGE_ARRAY and
C_PLB_ARD_NUM_CE_ARRAY) are unused.
The only channel transfer protocol supported at this time is the Xilinx Cachelink (XCL) interface. The
parameters to configure a Dynamic Address Generator (DAG) channel are unused and are only docu-
mented here for future reference.
If an XCL channel is connected to a master that will only perform read transactions, then the entry in
C_XCL_WRITEXFER_ARRAY should be set to 0 indicating that no write transfers will be performed.
This will reduce the channel logic to only contain logic for read transactions. Also, if an XCL channel is
connected to a master that can consume data as soon as its available, the entry in the
C_MCH_RDDATABUF_DEPTH_ARRAY for that channel should be set to zero. This will eliminate the
read data buffer and eliminate the latency that would normally exist in reading data from this buffer.
If the PLB slave interface is included in the design (C_INCLUDE_PLB_IPIF=1), care must be taken
when assigning User IP address ranges in the PLB Slave Interface generics. Since
C_PLB_ARD_ADDR_RANGE_ARRAY can contain address ranges for services internal to the PLB
Slave Burst and there may be address ranges within the User IP that will only be accessible through the
PLB, the C_MCH_USERIP_ADDRRANGE_ARRAY may be a subset of the
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DS626 April 24, 2009
Product Specification