DS626 Datasheet, PDF (17/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
A block diagram of a channel is shown in Figure 4.
X-Ref Target - Figure 4
MCH_Access_Ctrl(n)
MCH_Access_Data
(n*C_MCH_SIPIF_DWIDTH:
(n+1)*C_MCH_SIPIF_DWIDTH-1)
MCH_Access_Write(n)
MCH_Access_Full(n)
MCH_ReadData_Ctrl(n)
MCH_ReadData_Data
(n*C_MCH_SIPIF_DWIDTH:
(n+1)*C_MCH_SIPIF_DWIDTH-1)
MCH_ReadData_Exists(n)
MCH_ReadData_Read(n)
Access_Ctrl(n)
Access_Data
(n*C_MCH_SIPIF_DWIDTH:
(n+1)*C_MCH_SIPIF_DWIDTH-1)
Access_Exists(n)
Access_Read(n)
ReadData_Ctrl(n)
ReadData_Write(n)
ReadData_Full(n)
Chnl2IP
(n*C_MCH_SIPIF_DWIDTH/8:
(n+1)*C_MCH_SIPIF_DWIDTH/8-1)
MCH_ReadData_Data
(n*C_MCH_SIPIF_DWIDTH:
(n+1)*C_MCH_SIPIF_DWIDTH-1)
IPIC_Chnl_AddrAck(n)
MCH_ReadData_Data
(n*C_MCH_SIPIF_DWIDTH:
(n+1)*C_MCH_SIPIF_DWIDTH-1)
Chnl2IP_CS(n)
Chnl2IP_RNW(n)
Chnl2IP_Burst(n)
Chnl2IP_AddrValid(n)
IP2Chnl(n)
Timeout_Error(n)
Chnl_Reg(n)
Chnl_Reg(n)
ReadData_Data(n*C_MCH_SIPIF_DWIDTH: IP2Chnl_Data(n*C_MCH_SIPIF_DWIDTH:
(n+1)*C_MCH_SIPIF_DWIDTH-1)
(n+1)*C_MCH_SIPIF_DWIDTH-1)
Figure 4: Channel Interface Block Diagram
DS626_04_031809
Arbitration and Mux/De-Mux Logic
For the first phase of the MCH_PLBv46_Slave_Burst, only a fixed-priority arbitration scheme is sup-
ported. Requests from the MCH interfaces are indicated by internal signals output from the Channel
Logic. Requests from the PLB interface are indicated by the internal PLB2IP_CS signals output from the
PLBv46 Slave Burst.
To support memory controllers and other IP that support separate address and data phases, the
MCH_PLBv46_Slave_Burst provides a multiplexor/de-multiplexor for the IPIC address phase signals
and a separate multiplexor/de-multiplexor for data phase signals which are controlled by the arbitra-
tion logic.
Arbitration to determine the next transaction master occurs when the MCH_PLBv46_Slave_Burst is
idle. There are no channel or PLB requests or during the final transfers of the address phase of the active
transaction. Once a transaction is in progress, it will not be preempted to service a higher priority
request. However, when possible, arbitration will be overlapped with the final address transfers of the
active transaction to allow continuous access to the IP without any dead arbitration cycles.
DS626 April 24, 2009
www.xilinx.com
17
Product Specification