DS626 Datasheet, PDF (8/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
MCH_PLBv46_Slave_Burst Design Parameters
The MCH_PLBv46_Slave_Burst provides for tailoring of the core via VHDL generic parameters. These
parameters are detailed in Table 2.
Table 2: MCH_PLBv46_Slave_Burst Design Parameters
Generic
Feature /
Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
General
G1 Target FPGA family C_FAMILY
spartan3, spartan3e,
spartan3a,
spartan3an,
virtex4, qvirtex4,
qrvirtex4, virtex5
virtex5
string
G2
Include PLB
Interface
0 = don’t include PLB
C_INCLUDE_PlB_IPIF
IPIF
1
1 = include PLB IPIF
integer
Arbiter
G3 Arbitration Mode
C_PRIORITY_MODE⁽¹⁾
0 = fixed priority
mode
0
integer
Multi-channel Interface
G4
Number of channel
interfaces
C_NUM_CHANNELS
0-4
2
integer
Address width of
G5 plbv46/channel
C_MCH_SPLB_AWIDTH 32
interfaces
32
integer
G6
Address width of
slave interfaces
C_MCH_SIPIF_DWIDTH 32
32
integer
One entry for each
Array indicating the _{C_MCH_PROTOCOL}
channel. Allowed
G7
supported protocol
of each channel
_ARRAY ⁽²⁾
entries are:
{0}
0 = XCL protocol
integer
array
Array indicating the
address ranges of
User IP available to
MCH interfaces. The _{C_MCH_USERIP_}
G8
address ranges in
this array
correspond the to
ADDRRANGE
_ARRAY ^{(3) (4)}
Bus2IP_CS
generated from the
MCH interfaces.
Valid base address
and high address
pairs
User must
set values
SLV64_
ARRAY_
TYPE
Array indicating the
One entry for each
G9
depth of the Access C_MCH_ACCESSBUF_DE ^{channel. Allowed}
buffer for each
PTH_ARRAY
entries are:
{16}
integer
array
channel
4, 8, 16
Array indicating the
One entry for each
G10
depth of the
C_MCH_RDDATABUF
ReadData buffer for _{_DEPTH_ARRAY}⁽⁵⁾
channel. Allowed
entries are:
{16}
each channel
0,4, 8, 16
integer
array
8
www.xilinx.com
DS626 April 24, 2009
Product Specification