DS626 Datasheet, PDF (20/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
require a response on write transactions, but will wait for a entry into the ReadData buffer for a read
transaction.
Fixed Priority Mode
The fixed priority mode will be such that Channel 0 is the highest priority request, followed by Channel
1 through Channel N. Requests from the PLB interface will be the lowest priority. Priority of a channel
is set by its connection to the MCH_PLBv46_Slave_Burst.
Design Implementation
Target Technology
The intended target technology is the Virtex® and Spartan® FPGA families.
Device Utilization and Performance Benchmarks
Because the MCH_PLBv46_Slave_Burst is a module that will be used with other design modules in the
FPGA, the utilization and timing numbers reported in this section are just estimates. As the
MCH_PLBv46_Slave_Burst is combined with other pieces of the FPGA design, the utilization of FPGA
resources and timing will vary from the results reported here.
The MCH_PLBv46_Slave_Burst resource utilization for various parameter combinations measured
with Virtex-5 as a target device are detailed in Table 10.
Table 10: Performance and Resource Utilization Benchmarks on Virtex-5 (xc5vlx50-ff1153-1)
Parameter Values
Device Resources
Slice
Slice Flip-
Flops
Slice
LUTs
F_MAX ⁽¹⁾
0
1
1
1 32 32
0
1
68
104
122
209
0
1
1
1 32 32
0
0
55
134
127
223
0
1
1
1 32 32 16 0
101
187
180
200
1
1
2
1 32 32 16 0
187
398
480
213
1
1
4
1 32 32 16 0
204
399
484
200
2
2
4,4
1 32 32 16 0
309
541
627
202
2
2
4,4
1 64 32 16 0
345
542
628
200
20
www.xilinx.com
DS626 April 24, 2009
Product Specification