DS626 Datasheet, PDF (13/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
Table 3: Parameter-Port Dependencies (Cont’d)
Generic
or Port
Name
Affects Depends
Relationship Description
P25 Sl_rearbitrate
-
G2
Unused when C_INCLUDE_PLB_IPIF =
0.
P26 Sl_wrDAck
-
G2
Unused when C_INCLUDE_PLB_IPIF =
0.
P27 Sl_wrComp
-
G2
Unused when C_INCLUDE_PLB_IPIF =
0.
P28 Sl_wrBTerm
-
G2
Unused when C_INCLUDE_PLB_IPIF =
0.
P29 Sl_rdDBus
-
G2, G13
Unused when C_INCLUDE_PLB_IPIF =
0.
P30 Sl_rdDAck
-
G2
Unused when C_INCLUDE_PLB_IPIF =
0.
P31 Sl_rdComp
-
G2
Unused when C_INCLUDE_PLB_IPIF =
0.
P32 Sl_rdBTerm
-
G2
Unused when C_INCLUDE_PLB_IPIF =
0.
P33 Sl_rdWdAddr
-
G2
Unused when C_INCLUDE_PLB_IPIF =
0.
P34 Sl_MBusy
-
G2, G18
Unused when C_INCLUDE_PLB_IPIF =
0.
P35 Sl_MWrErr
-
G2, G18
Unused when C_INCLUDE_PLB_IPIF =
0.
P36 Sl_MRdErr
-
G2, G18
Unused when C_INCLUDE_PLB_IPIF =
0.
XCL Read Transfer Protocol
The protocol for cacheline read transfers via XCL is as follows:
The processor cache controller performs a single write to the Access buffer with the format shown in
Table 4 and waits for the data to be input into the ReadData buffer.
Table 4: Access Buffer Signals for Cacheline Read Transfer
MCH Access Signal
Value
MCH_Access_Control(n)
’0’
MCH_Access_Data(n*C_MCH_SIPIF_DWIDTH :
(n+1)*C_MCH_SIPIF_DWIDTH-1)
Memory address causing cache miss
When the cacheline data is available, it is written into the ReadData buffer with the format shown in
Table 5. The control bit in the ReadData buffer should be viewed as a "data valid" indicator. When ’1’,
the read operation occurred without error and the data is valid. When ’0’, the read operation had an
error or did not return a transfer acknowledge within the parameterizable time period and the data is
not valid. The data is returned in a target-word manner. This means that the data for the first address
DS626 April 24, 2009
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Product Specification