DS626 Datasheet, PDF (2/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
Functional Description
The MCH_PLBv46_Slave_Burst is designed to provide multiple channel interfaces and an optional PLB
interface to an IP core. The block diagram in Figure 1 shows an example use of the
MCH_PLBv46_Slave_Burst with an SDRAM, EMC, or DDR memory controller in a MicroBlaze™ sys-
tem.
X-Ref Target - Figure 1
XPS MCH SDRAM (DDR, EMC)
MCH PLBv46 Slave Burst
MCH Interface
MCH_0
IPIC_0
MicroBlaze
Processor
MCH_1
MCH_N
IPIC_1
Mux/
De-Mux
IPIC
IPIC_N
SDRAM
Memory Controller
External Memory
Controller (EMC)
DDR Memory
Controller
To External
Memories
PLB
Chnl_Status(0:N)
PLB2IP_CS
Retry/ToutSup
Channel Status
Registers
Legend:
Blocks in broken-line boxes are optional.
DS626_01_031809
Figure 1: MCH PLBV46 Slave Burst Block Diagram
The MCH_PLBv46_Slave_Burst consists of an optional PLB slave interface, a parameterizable number
of channel interfaces, arbitration logic to select between the channel interfaces and the PLB interface
and the appropriate multiplexors/de-multiplexors to connect the selected channel or PLB transaction
to the IP core. An optional timer can be included in the MCH_PLBv46_Slave_Burst to return an error if
the IP core does not return an acknowledge to a channel read transaction within a parameterizable
number of clocks.
Each channel consists of 2 buffers per channel, an Access buffer that contains the information about the
requested transaction, and a ReadData buffer that contains the resulting data from a Read transaction.
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DS626 April 24, 2009
Product Specification