English
Language : 

DS626 Datasheet, PDF (4/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers
Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
MCH_PLBv46_Slave_Burst I/O Signals
Table 1 provides a summary of all MCH_PLBv46_Slave_Burst input/output (I/O) signals, the inter-
faces under which they are grouped, and a brief description of the signal.
Table 1: MCH_PLBv46_Slave_Burst IO Descriptions
Port
Signal Name
Interface
I/O
Initial
State
Description
System
P1 SPLB_Clk
System I
- System clock.
P2 SPLB_Rst
System I
- System reset.
MCH Signals
P3
MCH_Access_Control(0:C_NUM_
CHANNELS-1)
MCH
I
Control signal to the Access buffers of
the channel interfaces. This signal
- indicates the type of access to be
performed (read or write) and the size
of the access (byte, halfword, or word).
MCH_Access_Data(0:C_NUM_
P4 CHANNELS*C_MCH_SIPIF_DWI
MCH
I
DTH-1)
Write Data to the Access buffers of the
- channel interfaces.
P5
MCH_Access_Write(0:C_NUM_C
HANNELS-1)
MCH
I
-
Write signals to Access buffers of the
channel interfaces.
P6 MCH_Access_Full(0:C_NUM
_CHANNELS-1)
MCH
O
0
Indicator that the Access buffers of the
channel interfaces are full.
MCH_ReadData_Control
P7 (0:C_NUM_CHANNELS-1)
Control signals for the ReadData
MCH
O
1
buffers of the channel interfaces.
These signals indicate if the data from
the ReadData buffer is valid.
MCH_ReadData_Data(0:C_MCH
P8 _SIPIF_DWIDTH*C_NUM_CHAN
NELS-1)
MCH
Read data from the ReadData buffers
O Zeros of the channel interfaces.
P9
MCH_ReadData_Read(0:C_NUM
_CHANNELS-1)
MCH
I
-
Read signals to the ReadData buffers
of the channel interfaces.
P10
MCH_ReadData_Exists(0:C_NU
M_CHANNELS-1)
MCH
O
0
Indicator that the ReadData buffers of
the channel interfaces are non-empty.
PLB Slave Signals
P11 PLB_ABus(0:31)
P12 PLB_PAValid
PLB Bus I
PLB Bus I
-
See table note(1).
-
See table note(1).
P13
PLB_masterID(0:C_SPLB_MID_
WIDTH-1)
PLB Bus
I
P14 PLB_RNW
PLB Bus I
-
See table note(1).
-
See table note(1).
P15
PLB_BE(0:[C_SPLB_DWIDTH/8]-
1)
PLB Bus
I
P16 PLB_MSize(0:1)
PLB Bus I
P17 PLB_size(0:3)
PLB Bus I
P18 PLB_type(0:2)
PLB Bus I
-
See table note(1).
-
See table note(1).
-
See table note(1).
-
See table note(1).
P19
PLB_wrDBus(0:C_SPLB_DWIDT
H-1)
PLB Bus
I
-
See table note(1).
P20 PLB_wrBurst
PLB Bus I
-
See table note(1).
4
www.xilinx.com
DS626 April 24, 2009
Product Specification