DS626 Datasheet, PDF (16/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
some arbitrary IP to demonstrate the XCL protocol. It is not meant to reflect exact response times of a
particular memory controller and should not be used to determine transaction latency or performance.
X-Ref Target - Figure 3
Clock
MCH_Access_Write(0)
MCH_Access_Control(0)
MCH_Access_Data[0:31]
MCH_Access_Full(0)
MCH_ReadData_Read(0)
MCH_ReadData_Control(0)
MCH_ReadData_Data[0:31]
MCH_ReadData_Exists(0)
Chnl0_Addr0 Chnl0_Data0 Chnl0_Data1 Chnl0_Data2 Chnl0_Data3
Assertion of MCH_Access_Full(0) depends on parameter setting of MCH(0) buffer size
Figure 3: XCL Cacheline Write
DS626_03_031809
Channel Block Diagram
The Channel Control block controls reading from the Access Buffer and writing to the ReadData Buffer.
It implements the decoding of the channel transfer protocol as determined by the
C_MCH_PROTOCOL_ARRAY. An address generator is provided for each channel which provides the
addressing sequence required by that channel. For XCL channels, the Address/BE Generation block
generates the intermediate cacheline addresses in a manner to support target-word first accesses. The
IPIC Interface block implements the necessary IPIC signal protocol and timing to communicate with
the IP Core.
As there is a request in the Access Buffer, the Channel Control logic reads the transaction request from
the Access Buffer, decodes the request, loads the address generator, and starts the IPIC interface logic.
At this point, the IPIC transaction is ready and waiting for the Arbitration Logic to grant this channel
access to the IP core. The goal is to have be no wasted cycles after arbitration.
When the arbitration logic selects this channel to have access to the IP core, the IPIC signal protocol pro-
vides the necessary handshaking to complete the transaction. For a read transaction, the Channel Con-
trol block will write the cacheline data into the ReadData buffer. If a timeout occurs, the Channel
Control block writes the appropriate values into the ReadData buffer and terminates the transaction.
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DS626 April 24, 2009
Product Specification