DS626 Datasheet, PDF (3/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
A cacheline access is requested by writing the transaction information into the Access Buffer of the
channel. The Channel Logic monitors this buffer, gets the transaction from the Access Buffer, then con-
verts it to the proper IPIC signals. The Arbitration Logic monitors the channel interfaces and the PLB
interface and arbitrates between the pending transactions. Based on the arbitration scheme chosen, the
highest priority transaction is passed through the IPIC Mux/DeMux block to the attached IP. The IPIC
responses are passed back to the appropriate channel or to the PLB Slave Burst.
The advantage of having Channel Logic for each channel is that arbitration is done on the IPIC signal
set, thus there is no delay after arbitration for decoding of the channel signals into the appropriate IPIC
signals. An additional advantage is that the logic to generate the addresses for the channel is parame-
terized to only provide the addressing scheme required by that channel and there is no delay in dynam-
ically loading and switching the address generation mode.
In the example system shown in Figure 1, the Microblaze processor has two MCH interfaces – one for
the instruction cache and one for the data cache. Both of these channels would have be set to have the
XCL protocol. Because the instruction cache performs read transactions only and will consumes data as
soon as it is available, set the entry in C_XCL_WRITEXFER_ARRAY for this channel to 0, no write
transfers. Also, set the entry in C_MCH_RDDATABUF_DEPTH_ARRAY to zero so that there will be no
additional latency in reading data from a buffer when it is available.
PLB Slave Interface
The PLB Slave Interface is provided by the PLBv46 Slave Burst IP Core described in DS562 PLBv46
Slave Burst V1.00.a Product Specification and will not be described in this document. Note that the IPIC
signal protocol implemented by the MCH_PLBv46_Slave_Burst is also described in DS562 PLBv46
Slave Burst V1.00.a Product Specification. The PLBv46 Slave Burst IP Core will be configured in a Slave-
only mode utilizing only those portions of the PLBv46 Slave Burst required for attachment to the cur-
rent memory controller cores. If the optional Timeout/Error logic is included in the design, the output
from this logic can generate an interrupt, utilizing the interrupt service provided by the PLBv46 Slave
Burst.
Xilinx Multi-Channel (MCH) Interfaces
Each channel can be configured to support the Xilinx Cachelink (XCL) protocol.
XCL channels are designed to interface to processors for cacheline accesses to and from memory. An
XCL channel only performs cacheline read transactions of length C_MCH_CACHESIZE_ARRAY(n).
Write transactions are configured by the C_XCL_WRITE_XFERS_ARRAY. If the XCL channel is con-
nected to an Instruction Cache which would not perform write transfers, then
C_XCL_WRITE_XFERS_ARRAY(n) = 0. All write transactions are single writes when
C_XCL_WRITEXFERS_ARRAY(n) = 1. All write transactions are cacheline write transactions of length
C_XCL_LINESIZE_ARRAY(n) when C_XCL_WRITEXFERS_ARRAY(n) = 2. Cacheline read and cache-
line write transactions are always word-width transfers. Single writes can be byte, half-word, and
word-width transfers.
DS626 April 24, 2009
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Product Specification