DS626 Datasheet, PDF (15/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
Table 6: Access Buffer Signals for Single Write Transfer - First Write
MCH Access Signal
Value
"00"
"01"
If byte write
"10"
MCH_Access_Data((n+1)*C_MCH_SIPIF_DWIDTH-2):
(n+1)*C_MCH_SIPIF_DWIDTH-1)
"11"
"01"
If half-word write
"11"
If word write
"00"
Table 7: Access Buffer Signals for Single Write Transfer - Second Write
MCH Access Signal
Value
MCH_Access_Control(n)
If byte write
’1’
If half-word or word write ’0’
MCH_Access_Data(n*C_MCH_SIPIF_D
WIDTH: (n+1)*C_MCH_SIPIF_DWIDTH-
1)
If byte write
If half-word write
If word write
valid data byte in correct byte lane
valid data half-word in correct byte lanes
word value
XCL Cacheline Write Transfer Protocol (C_XCL_WRITEXFER_ARRAY(n)=2)
The protocol for cacheline write transfers via MCH is as follows:
The cache controller performs a series of writes into the Access buffer. There is no return status or value.
The first write provides the starting address of the cacheline and the remaining writes provide the data
to be written. The writes into the Access buffer must occur on each clock. There can be no gaps in the
writing of data into the Access buffer. The format of these writes is shown in Table 8 and Table 9.
Table 8: Access Buffer Signals for Cacheline Write Transfer - First Write
MCH Access Signal
Value
MCH_Access_Control(n)
’1’
MCH_Access_Data(n*C_MCH_SIPIF_DWIDTH: (n+1)*C_MCH_SIPIF_DWIDTH-1) Word aligned address
Table 9: Access Buffer Signals for Cacheline Write Transfer - Remaining writes
MCH Access Signal
Value
MCH_Access_Control(n)
’1’
MCH_Access_Data(n*C_MCH_SIPIF_DWIDTH: (n+1)*C_MCH_SIPIF_DWIDTH-1) cacheline word value
Figure 3 shows the timing diagram for a XCL Cacheline Write. Note that the writes into the Access
buffer occur on every clock once the first write has occurred. There can be no gaps in writing data into
the Access buffer. The diagram is provided to indicate relative timing and example responses from
DS626 April 24, 2009
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Product Specification