DS626 Datasheet, PDF (21/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
Table 10: Performance and Resource Utilization Benchmarks on Virtex-5 (xc5vlx50-ff1153-1) (Cont’d)
4
2
4,4
1 128 32 16 0
553
820
1120
200
4
4 4,4,4,4 1 32 32 16 0
510
809
1127
203
4
4 4,4,4,4 0 32 32 16 0
423
561
882
200
1. F_MAX represents the maximum frequency of the MCH_PLBv46_Slave_Burst in a standalone configuration. The actual maximum fre-
quency will depend on the entire system and may be greater or less than what is recorded in this table.
Reference Documents
The following documents contain reference information important to understanding the Xilinx
MCH_PLBv46_Slave_Burst design.
1. DS562, PLBv46_Slave_Burst V1.00.A Product Specification
2. IBM CoreConnect 128-Bit Local Peripheral Bus, Architectural Specification (v4.6)
Support
Xilinx provides technical support for this LogiCORE IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Revision History
The following table shows the revision history for this document.
Date
5/25/07
7/28/08
9/29/08
4/24/09
Version
1.0
1.1
1.2
1.3
Description of Revisions
Initial Xilinx release.
Added QPro Virtex-4 Hi-Rel and QPro Virtex-4 Rad Tolerant FPGA support.
Incorporated CR473185; updated PDF properties; corrected link in Ref Docs
section.
Replaced references to supported device families and tool names with hyperlink
to PDF file.
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DS626 April 24, 2009
www.xilinx.com
21
Product Specification